Cargando…
The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS
A clock and data recovery IP, the eCDR, is presented which is intended to be implemented on the detector front-end ASICs that need to communicate with the GBTX by means of e-links. The programmable CDR accepts data at 40, 80, 160 or 320Mbit/s and generates retimed data as well as 40, 80, 160 and 320...
Autores principales: | Tavernier, Filip, Bonacini, S, Francisco, R, Moreira, P, Poltorak, K |
---|---|
Publicado: |
2013
|
Materias: | |
Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/8/12/C12024 http://cds.cern.ch/record/1709948 |
Ejemplares similares
-
An 8-channel programmable 80/160/320 Mbit/s radiation-hard phase-aligner circuit in 130-nm CMOS
por: Tavernier, F, et al.
Publicado: (2012) -
The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis
por: Leitao, P, et al.
Publicado: (2015) -
Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2021) -
Design and characterization of an SEU-robust register in 130nm CMOS for application in HEP ASICs
por: Bonacini, S
Publicado: (2010) -
A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS
por: Poltorak, K, et al.
Publicado: (2012)