LHCb: Dynamically Adaptive Header Generator and Front-End Source Emulator for a 100 Gbps FPGA Based DAQ

The proposed upgrade for the LHCb experiment envisages a system of 500 Data sources each generating data at 100 Gbps, the acquisition and processing of which is a big challenge even for the current state of the art FPGAs. This requires an FPGA DAQ module that not only handles the data generated by the experiment but also is versatile enough to dynamically adapt to potential inadequacies of other components like the network and PCs. Such a module needs to maintain real time operation while at the same time maintaining system stability and overall data integrity. This also creates a need for a Front-end source Emulator capable of generating the various data patterns, that acts as a testbed to validate the functionality and performance of the Header Generator. The rest of the abstract briefly describes these modules and their implementation. The Header Generator is used to packetize the streaming data from the detectors before it is sent to the PCs for further processing. This is achieved by continuously scanning the input stream for payload length information, extracting the same and then assembling the header. Since the payloads(events) are of varying lengths, the starting position of each new payload is calculated in real time based on the length information of the preceding payload. After a fixed number of the payloads have passed and their length information extracted and added to the header template, additional information like the total number of events in the packet, size of the largest payload, and also the combined length of the sum of all payloads and the header itself are calculated and added to the header template. This process completes the generation of a single Header. Signals are asserted to indicate that the header is ready to be read out and sent to the PC. Two sets of memories were created so that the assembling of the next header can begin while the calculation of the additional information for the previous header are still under way. A mechanism to dynamically invalidate individual events were added to deal with downstream bottlenecks that could result in buffer overflows compromising data integrity. This drops much of the individual payloads in a controlled manner, marking the corresponding header field as invalid, effectively reducing the data rate to a trickle on the fly, while maintaining system stability and overall data integrity. The Source Emulator serves the dual purpose of being a test bench to the Header Generator as well as being an stand alone module that can be used in any other system where the detector data needs to emulated. The variability of the detector data is modeled by using a pseudo-random number generator to create payloads of varying lengths. With this Source Emulator as the test bench the Header Generator was functionally validated both for general scenarios as well as for identified corner cases. We present simulation results and performance measures from implementation on a Altera Stratix IV platform.