Associative Memory computing power and its simulation.

The associative memory (AM) chip is ASIC device specifically designed to perform ``pattern matching'' at very high speed and with parallel access to memory locations. The most extensive use for such device will be the ATLAS Fast Tracker (FTK) processor, where more than 8000 chips will be installed in 128 VME boards, specifically designed for high throughput in order to exploit the chip's features. Each AM chip will store a database of about 130000 pre-calculated patterns, allowing FTK to use about 1 billion patterns for the whole system, with any data inquiry broadcast to all memory elements simultaneously within the same clock cycle (10 ns), thus data retrieval time is independent of the database size. Speed and size of the system are crucial for real-time High Energy Physics applications, such as the ATLAS FTK processor. Using 80 million channels of the ATLAS tracker, FTK finds tracks within 100 $\mathrm{\mu s}$. The simulation of such a parallelized system is an extremely complex task when executed in commercial computers based on normal CPUs. The algorithm performance is limited on CPU, due to the lack of parallelism, with the additional issue of the very large memory requirement. In fact the AM chip uses a content addressable memory (CAM) architecture. We report on the organization of the simulation into multiple jobs to satisfy the memory constraints and on the optimization performed to reduce the processing time. Finally, we introduce the idea of a new computing unit based on a small number of AM chips that could be plugged inside commercial PCs as coprocessors. This unit would both satisfy the need for very large memory and significantly reduce the simulation time due to the use of the highly parallelized AM chips.