Vertex-Detector R&D for CLIC

A detector concept based on hybrid pixel-detector technology is under development for the CLIC vertex detector. It comprises fast, low-power and small-pitch readout ASICs implemented in 65 nm CMOS technology (CLICpix) coupled to ultra-thin sensors (planar or active HV-CMOS) via low-mass interconnects. The power dissipation of the readout chips is reduced by means of power pulsing, allowing for a cooling system based on forced air flow. In this contribution the CLIC vertex-detector requirements are reviewed and the current status of R&D on readout and sensors is presented.