The ATLAS FTK system: how to improve the physics potential with a tracking trigger

After a very successful data taking run, the ATLAS experiment [1] is being upgraded to cope with the higher luminosity and higher center of mass energy that the Large Hadron Collider (LHC) will provide in the next years. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device processor based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGAs) form an important part of the system architecture, and the large level of computing power required for pattern recognition is provided by incorporating standard-cell ASICs named Associative Memory (AM). FTK provides global track reconstruction in the full inner silicon detector, with resolution comparable to the offline algorithms, in approximately 100 microseconds, allowing a fast and precise detection of the primary and secondary vertex information. The track and vertex information is then used by the high-level trigger (HLT) algorithms, allowing highly improved trigger performance for the most dicult signatures, such as b-jets. The architecture of the FTK system and the expected physics performance in the harsh environment at high pile-up and high luminosities expected for LHC run2 are presented.