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SVA: the power of assertions in SystemVerilog
This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides...
| Autores principales: | , , , |
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| Lenguaje: | eng |
| Publicado: |
Springer
2015
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1007/978-3-319-07139-8 http://cds.cern.ch/record/1967936 |