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Digital integrated circuit design using Verilog and SystemVerilog

For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of de...

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Autor principal: Mehler, Ronald W
Lenguaje:eng
Publicado: Elsevier Science 2014
Materias:
Acceso en línea:http://cds.cern.ch/record/1967980
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author Mehler, Ronald W
author_facet Mehler, Ronald W
author_sort Mehler, Ronald W
collection CERN
description For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually
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institution Organización Europea para la Investigación Nuclear
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publishDate 2014
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spelling cern-19679802021-04-21T20:50:45Zhttp://cds.cern.ch/record/1967980engMehler, Ronald WDigital integrated circuit design using Verilog and SystemVerilogComputing and Computers For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually Elsevier Scienceoai:cds.cern.ch:19679802014
spellingShingle Computing and Computers
Mehler, Ronald W
Digital integrated circuit design using Verilog and SystemVerilog
title Digital integrated circuit design using Verilog and SystemVerilog
title_full Digital integrated circuit design using Verilog and SystemVerilog
title_fullStr Digital integrated circuit design using Verilog and SystemVerilog
title_full_unstemmed Digital integrated circuit design using Verilog and SystemVerilog
title_short Digital integrated circuit design using Verilog and SystemVerilog
title_sort digital integrated circuit design using verilog and systemverilog
topic Computing and Computers
url http://cds.cern.ch/record/1967980
work_keys_str_mv AT mehlerronaldw digitalintegratedcircuitdesignusingverilogandsystemverilog