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Scintillating Fibre Tracker Front-End Electronics for LHCb upgrade

The LHCb detector will be upgraded during the next LHC shutdown in 2018/19. The tracker system will undergo major changes. Its components will be replaced by new technologies in order to cope with the increased hit occupancy and the higher radiation dose. A detector made of scintillating fibres read...

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Detalles Bibliográficos
Autor principal: Comerma, A
Lenguaje:eng
Publicado: 2014
Acceso en línea:http://cds.cern.ch/record/1969526
Descripción
Sumario:The LHCb detector will be upgraded during the next LHC shutdown in 2018/19. The tracker system will undergo major changes. Its components will be replaced by new technologies in order to cope with the increased hit occupancy and the higher radiation dose. A detector made of scintillating fibres read out by silicon photomultipliers (SiPM) is envisaged for this upgrade. Even if this technology has proven to achieve high efficiency and spatial resolution, its integration within a LHC experiment bears new challenges. The detector will consist of 12 planes of 5 to 6 layers of 250μm fibres stacked covering a total area of 5x6m^2 . The desired spacial resolution on the reconstructed hit is 100μm. SiPMs have been adapted to the detector geometry reducing the dead area between channels. A total of 64 channels are arranged in a single die with common cathode connection and channel size of 0.23x1.32mm^2 . Two dies are packaged together with only 0.25mm of dead area between them. Radiation tolerance of such devices is an important challenge. Operation at low temperatures will be crucial to achieve the desired performance. Several manufacturers have produced prototypes for testing with different characteristics but same form factor. This size leads to a total of over 500k channels which need to be read out at 40MHz. The PACIFIC ASIC will readout of SiPMs with no interface components between devices and ASIC. It will handle 64 channels with analog signal processing and digitization. Current prototype comprises 8 channels. The first stage is a current conveyor followed by a fast shaper (≈10ns to cope with signal arrival times) and a gated integrator. The digitization is done using a 2 bits non-linear flash ADC operating at 40MHz. The power consumption has been kept bellow 8mW per channel.