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Upgrade of the ATLAS Tile Calorimeter

The Tile Calorimeter (TileCal) is the main hadronic calorimeter covering the central region of the ATLAS experiment at LHC. TileCal readout consists of about 10000 channels. The bulk of its upgrade will occur for the High Luminosity LHC operation (Phase 2 around 2023) where the peak luminosity will...

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Detalles Bibliográficos
Autores principales: Reed, Robert, ATLAS Tile Collaboration
Lenguaje:eng
Publicado: 2014
Materias:
Acceso en línea:http://cds.cern.ch/record/1975519
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author Reed, Robert
ATLAS Tile Collaboration
author_facet Reed, Robert
ATLAS Tile Collaboration
author_sort Reed, Robert
collection CERN
description The Tile Calorimeter (TileCal) is the main hadronic calorimeter covering the central region of the ATLAS experiment at LHC. TileCal readout consists of about 10000 channels. The bulk of its upgrade will occur for the High Luminosity LHC operation (Phase 2 around 2023) where the peak luminosity will increase 5x compared to the design luminosity (10^{34} cm^{-2}s^{-1}) but with maintained energy (i.e. 7+7 TeV). The TileCal upgrade aims to replace the majority of the on- and off-detector electronics so that all calorimeter signals can be digitized and directly sent to the off-detector electronics in the counting room. This will reduce pile-up problems and allow more complex trigger algorithms. To achieve the required reliability, redundancy has been introduced at different levels. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. 10 Gbps optical links are used to read out all digitized data to the counting room while 4.8 Gbps down-links are used for control, synchronization and configuration of the on-detector Field Programmable Gate Arrays (FPGAs). To provide sufficient radiation tolerance, the latter use scrubbing and partial reconfiguration. For the off-detector electronics a pre-processor (sROD) is being developed, which takes care of the initial trigger processing while temporarily storing the main data flow in pipeline and de-randomizer memories. FPGAs are extensively used for the logic functions off- and on-detector. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, is planned to be inserted in ATLAS in the end of 2015.
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institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2014
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spelling cern-19755192019-09-30T06:29:59Zhttp://cds.cern.ch/record/1975519engReed, RobertATLAS Tile CollaborationUpgrade of the ATLAS Tile CalorimeterParticle Physics - ExperimentThe Tile Calorimeter (TileCal) is the main hadronic calorimeter covering the central region of the ATLAS experiment at LHC. TileCal readout consists of about 10000 channels. The bulk of its upgrade will occur for the High Luminosity LHC operation (Phase 2 around 2023) where the peak luminosity will increase 5x compared to the design luminosity (10^{34} cm^{-2}s^{-1}) but with maintained energy (i.e. 7+7 TeV). The TileCal upgrade aims to replace the majority of the on- and off-detector electronics so that all calorimeter signals can be digitized and directly sent to the off-detector electronics in the counting room. This will reduce pile-up problems and allow more complex trigger algorithms. To achieve the required reliability, redundancy has been introduced at different levels. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. 10 Gbps optical links are used to read out all digitized data to the counting room while 4.8 Gbps down-links are used for control, synchronization and configuration of the on-detector Field Programmable Gate Arrays (FPGAs). To provide sufficient radiation tolerance, the latter use scrubbing and partial reconfiguration. For the off-detector electronics a pre-processor (sROD) is being developed, which takes care of the initial trigger processing while temporarily storing the main data flow in pipeline and de-randomizer memories. FPGAs are extensively used for the logic functions off- and on-detector. One hybrid demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, is planned to be inserted in ATLAS in the end of 2015.ATL-TILECAL-SLIDE-2014-832oai:cds.cern.ch:19755192014-12-09
spellingShingle Particle Physics - Experiment
Reed, Robert
ATLAS Tile Collaboration
Upgrade of the ATLAS Tile Calorimeter
title Upgrade of the ATLAS Tile Calorimeter
title_full Upgrade of the ATLAS Tile Calorimeter
title_fullStr Upgrade of the ATLAS Tile Calorimeter
title_full_unstemmed Upgrade of the ATLAS Tile Calorimeter
title_short Upgrade of the ATLAS Tile Calorimeter
title_sort upgrade of the atlas tile calorimeter
topic Particle Physics - Experiment
url http://cds.cern.ch/record/1975519
work_keys_str_mv AT reedrobert upgradeoftheatlastilecalorimeter
AT atlastilecollaboration upgradeoftheatlastilecalorimeter