Simulation of a macro-pipelined multi-cpu event processor for use in FASTBUS

Detalles Bibliográficos
Autores principales: Letheren, M F, Marchioro, A, Slorach, F
Lenguaje:eng
Publicado: 1989
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/23.41111
http://cds.cern.ch/record/197655
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author Letheren, M F
Marchioro, A
Slorach, F
author_facet Letheren, M F
Marchioro, A
Slorach, F
author_sort Letheren, M F
collection CERN
id cern-197655
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 1989
record_format invenio
spelling cern-1976552019-09-30T06:29:59Zdoi:10.1109/23.41111http://cds.cern.ch/record/197655engLetheren, M FMarchioro, ASlorach, FSimulation of a macro-pipelined multi-cpu event processor for use in FASTBUSDetectors and Experimental TechniquesCERN-DD-89-19LAA-RT-89-02oai:cds.cern.ch:1976551989
spellingShingle Detectors and Experimental Techniques
Letheren, M F
Marchioro, A
Slorach, F
Simulation of a macro-pipelined multi-cpu event processor for use in FASTBUS
title Simulation of a macro-pipelined multi-cpu event processor for use in FASTBUS
title_full Simulation of a macro-pipelined multi-cpu event processor for use in FASTBUS
title_fullStr Simulation of a macro-pipelined multi-cpu event processor for use in FASTBUS
title_full_unstemmed Simulation of a macro-pipelined multi-cpu event processor for use in FASTBUS
title_short Simulation of a macro-pipelined multi-cpu event processor for use in FASTBUS
title_sort simulation of a macro-pipelined multi-cpu event processor for use in fastbus
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1109/23.41111
http://cds.cern.ch/record/197655
work_keys_str_mv AT letherenmf simulationofamacropipelinedmulticpueventprocessorforuseinfastbus
AT marchioroa simulationofamacropipelinedmulticpueventprocessorforuseinfastbus
AT slorachf simulationofamacropipelinedmulticpueventprocessorforuseinfastbus

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