The CMS pixel readout chip for the Phase 1 Upgrade

The present CMS pixel Read Out Chip (ROC) was designed for operation at a bunch spacing of 25\,ns and to be efficient up to the nominal instantaneous luminosity of 10$^{34} \rm cm^{-2} \rm s^{-1}$. Based on the excellent LHC performance to date and the upgrade plans for the accelerators, it is anticipated that the instantaneous luminosity could reach $2\times10^{34} \rm cm^{-2} \rm s^{-1}$ before the Long Shutdown 2 (LS2) in 2018, and well above this by the LS3 in 2022. That is why a new ROC has been designed and why a completely new pixel detector will be built with a planned installation in CMS during an extended winter shutdown in 2016/17. The ROC for the upgraded pixel detector is an evolution of the present architecture. It will be manufactured in the same 250\,nm CMOS process. The core of the architecture is maintained, with enhancement in performance in three main areas: readout protocol, reduced data loss and enhanced analog performance. The main features of the new CMS pixel ROC are presented together with measured performance of the chip.