Cargando…

Validation of second set of IP blocks

Detalles Bibliográficos
Autor principal:	Martin Chassard, G.
Formato:	info:eu-repo/semantics/article
Lenguaje:	eng
Publicado:	2015
Materias:	Detectors and Experimental Techniques 3: Microelectronics and interconnection technology 3.3: Shareable IP Blocks for HEP
Acceso en línea:	http://cds.cern.ch/record/1987730

Ejemplares similares

Validation of first set of IP blocks
por: Re, V.
Publicado: (2015)

2nd set of macro blocks
por: Martin-Chassard, G.
Publicado: (2014)

1st set of macro blocks
por: Re, V.
Publicado: (2014)

Development of variable sampling rate, low power 10-bit SAR ADC in 130 nm IBM technology
por: Moron, J, et al.
Publicado: (2015)

Pixel front-end development in 65 nm CMOS technology
por: Havránek, M, et al.
Publicado: (2014)

A 10MS/s 8-bit charge-redistribution ADC for hybrid pixel applications in 65m CMOS
por: Kishishita, T, et al.
Publicado: (2013)

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II
por: Kishishita, T, et al.
Publicado: (2013)

SEU tolerant memory design for the ATLAS pixel readout chip
por: Menouni, M, et al.
Publicado: (2013)

Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade
por: Backhaus, M
Publicado: (2012)

The Shunt-LDO regulator to power the upgraded ATLAS pixel detector
por: Gonella, L, et al.
Publicado: (2012)

The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project
por: Zivkovic, V, et al.
Publicado: (2012)

A fast, low-power, 6-bit SAR ADC for readout of strip detectors in the LHCb Upgrade experiment.
por: Firlej, M, et al.
Publicado: (2014)

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips
por: Marconi, S., et al.
Publicado: (2014)

Characterization of a commercial 65 nm CMOS technology for SLHC applications
por: Bonacini, S, et al.
Publicado: (2012)

A test beam set-up for the characterization of the Geiger-mode avalanche photodiode technology for particle tracking
por: Vilella, A, et al.
Publicado: (2012)

Enable access to 3D interconnection technology
por: Moser, H-G.
Publicado: (2015)

Assessment of 3D integrated sensors
por: Moser, H.-G.
Publicado: (2015)

Status and perspectives of pixel sensors based on 3D vertical integration
por: Re, V
Publicado: (2014)

CMOS MAPS in a Homogeneous 3D Process for Charged Particle Tracking
por: Manazza, A, et al.
Publicado: (2014)

Production and characterization of SLID interconnected n-in-p pixel modules with 75 micron thin silicon sensors
por: Andricek, L, et al.
Publicado: (2014)

3D integration of Geiger-mode avalanche photodiodes aimed to very high fill-factor pixels for future linear colliders
por: Vilella, E, et al.
Publicado: (2013)

Production and characterisation of SLID interconnected n-in-p pixel modules with 75 μm thin silicon sensors
por: Andricek, L, et al.
Publicado: (2014)

Test results of the first 3D-IC prototype chip developed in the framework of HL-LHC/ATLAS hybrid pixel upgrade
por: Pangaud, P, et al.
Publicado: (2014)

Flip chip assembly of thinned chips for hybrid pixel detector applications
por: Fritzsch, T, et al.
Publicado: (2014)

Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC
por: Aruntinov, D, et al.
Publicado: (2013)

Component Processing
por: Re, V.
Publicado: (2013)

Geiger-Mode Avalanche Photodiodes in Particle Detection
por: Vilella, E, et al.
Publicado: (2012)

Recent progress in the development of 3D deep n-well CMOS MAPS
por: Traversi, Gianluca, et al.
Publicado: (2012)

The SuperB Silicon Vertex Tracker and 3D vertical integration
por: Re, Valerio
Publicado: (2011)

ORGANISATION OF THE 3D PRODUCTION
por: Re, Valerio
Publicado: (2012)

PRODUCTION OF DEDICATED SENSORS
por: Moser, Hans-Günther
Publicado: (2012)

AVAILABILITY OF WAFERS OF ASIC ELECTRONICS
por: Valerio, Re
Publicado: (2012)

WAFER POSTPROCESSING (THINNING, TSV)
por: Moser, Hans-Gunther
Publicado: (2013)

QUALIFICATION OF ASIC AND SENSORS FOR 3D INTERCONNECTION
por: Re, Valerio
Publicado: (2013)

Test interconnection and evaluation:
por: Re, V.
Publicado: (2014)

Development of active edge pixel sensors and four-side buttable modules using vertical integration technologies
por: Macchiolo, A., et al.
Publicado: (2013)

3D interconnection processing accomplished
por: Re, V.
Publicado: (2014)

Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2⋅10 15 $n_{eq}$ /cm 2
por: Weigell, P, et al.
Publicado: (2011)

Development of scalable frequency and power Phase-Locked Loop in 130nm CMOS technology
por: Firlej, M, et al.
Publicado: (2014)

Perspectives of 65 nm CMOS technologies for high performance front-end electronics
por: Traversi, G, et al.
Publicado: (2014)

Cannot write session to /tmp/vufind_sessions/sess_9bbqig8c8g1itoof0siv7akdmk