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Pixel front-end development in 65 nm CMOS technology

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micr...

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Detalles Bibliográficos
Autores principales: Havránek, M, Hemperek, T, Kishishita, T, Krüger, H, Wermes, N
Formato: info:eu-repo/semantics/article
Lenguaje:eng
Publicado: JINST 2014
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/9/01/C01003
http://cds.cern.ch/record/1997604
Descripción
Sumario:Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed.