The FE-I4 pixel readout system-on-chip resubmission for the insertable B-Layer project

The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications an...

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Detalles Bibliográficos
Autores principales: Zivkovic, V, Schipper, J.D, Garcia-Sciveres, M, Mekkaoui, A, Barbero, M, Darbo, G, Gnani, D, Hemperek, T, Menouni, M, Fougeron, D, Gensolen, F, Jensen, F, Caminada, L, Gromov, V, Kluit, R, Fleury, J, Krüger, H, Backhaus, M, Fang, X, Gonella, L, Rozanove, A, Arutinov, D
Formato: info:eu-repo/semantics/article
Lenguaje:eng
Publicado: JINST 2012
Materias:
Detectors and Experimental Techniques
3: Microelectronics and interconnection technology
3.3: Shareable IP Blocks for HEP
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/7/02/C02050
http://cds.cern.ch/record/1997628
Descripción
Sumario:The FE-I4 is a new pixel readout integrated circuit designed to meet the requirements of ATLAS experiment upgrades. The first samples of the FE-I4 engineering run (called FE-I4A) delivered promising results in terms of the requested performances. The FE-I4 team envisaged a number of modifications and fine-tuning before the actual exploitation, planned within the Insertable B-Layer (IBL) of ATLAS. As the IBL schedule was pushed significantly forward, a quick and efficient plan had to be devised for the FE-I4 redesign. This article will present the main objectives of the resubmission, together with the major changes that were a driving factor for this redesign. In addition, the top-level verification and test efforts of the FE-I4 will also be addressed.

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