L1Track: a fast Level 1 track trigger for the ATLAS High Luminosity Upgrade

With the planned high-luminosity upgrade of the LHC (HL-LHC), the ATLAS detector will see its collision rate increase by approximately a factor of 5 with respect to the current LHC operation. The earliest hardware based ATLAS trigger stage ("Level 1") will have to provide an higher rejection factor in a more difficult environment: a new improved Level 1 trigger architecture is under study, which includes the possibility of extracting with low latency and hight accuracy tracking information on time for the decision taking process. The expected trigger rates at HL-LHC and the available latency are the key ingredients that will drive the new design. The Level 1 track trigger (L1Track) design requires substantial modification of the ATLAS silicon detector readout philosophy: a precursor of the potential merging of detector and trigger architectures in the future silicon detectors at particle colliders. We will discuss potential approaches that are being actively considered to fulfil the demanding HL-LHC constraints and deliver tracks of quality sufficient to maintain trigger rejection power with a very limited time budget.