Energy Reconstruction and high-speed Data Transmission with FPGAs for the Upgrade of the ATLAS Liquid Argon Calorimeter at LHC

The Liquid Argon calorimeter of the ATLAS detector at CERN near Geneva is equipped with improved readout and trigger electronics for the operation at higher luminosity LHC in the frame of several upgrades (Phase-0, I, and II). Special attention is given to an early digitisation of detector raw data and their following digital data transmission and processing via FPGAs already for the Level-1 trigger. The upgrades additionally foresee to provide higher spatial granularity information for the Level-1 trigger in order to improve its performance for low momentum single particles at increased collision rates. The first part of this dissertation contains the development and implementation of a modular detector simulation framework, AREUS, which allows to analyse different filter algorithms for the energy reconstruction as well as their performance with respect to the expected digitised detector raw data. In this detector simulation framework the detailed algorithmic functionality of the FPGAs has been taken into account. Various filter algorithms, especially the Optimal Filter and a Wiener Filter with Forward Correction, are discussed with regard to their performance in energy reconstruction of the future Liquid Argon calorimeter trigger system. In the second part of this thesis, the high-speed data transfer for the acquisition of the trigger data is being developed. For this purpose, a generic 10 Gigabit Ethernet UDP stack is designed in VHDL, that is currently applied in an ALTERA® Stratix-IV FPGA as part of the readout electronics of a demonstrator setup in the context of the Phase-0 Upgrade. After implementation in a prototype electronics board, data transfer from the detector front-end is realised. A successful test in the demonstrator setup installed in the ATLAS detector verifying the correct transmission of the Liquid Argon calorimeter trigger signals concludes this work.