Readout Architecture for Hybrid Pixel Readout Chips

The original contribution of this thesis to knowledge are novel digital readout architectures for hybrid pixel readout chips. The thesis presents asynchronous bus-based architecture, a data-node based column architecture and a network-based pixel matrix architecture for data transportation. It is shown that the data-node architecture achieves readout efficiency 99 % with half the output rate as a bus-based system. The network-based solution avoids ``broken'' columns due to some manufacturing errors, and it distributes internal data traffic more evenly across the pixel matrix than column-based architectures. An improvement of $>$ 10 % to the efficiency is achieved with uniform and non-uniform hit occupancies. Architectural design has been done using transaction level modeling ($TLM$) and sequential high-level design techniques for reducing the design and simulation time. It has been possible to simulate tens of column and full chip architectures using the high-level techniques. A decrease of $>$ 10 in run-time is observed using these techniques compared to register transfer level $(RTL)$ design technique. Reduction of 50 % for lines-of-code ($LoC$) for the high-level models compared to the $(RTL)$ description has been achieved. Two architectures are then demonstrated in two hybrid pixel readout chips. The first chip, Timepix3 has been designed for the Medipix3 collaboration. According to the measurements, it consumes $<$ 1 W/cm$^2$. It also delivers up to 40 Mhits/s/cm$^2$ with 10-bit time-over-threshold ($ToT$) and 18-bit time-of-arrival ($ToA$) of 1.5625 ns. The chip uses a token-arbitrated, asynchronous two-phase handshake column bus for internal data transfer. It has also been successfully used in a multi-chip particle tracking telescope. The second chip, VeloPix, is a readout chip being designed for the upgrade of Vertex Locator ($VELO$) of the LHCb experiment at CERN. Based on the simulations, it consumes $<$ 1.5 W/cm$^2$ while delivering up to 320 Mpackets/s/cm$^2$, each packet containing up to 8 pixels. VeloPix uses a node-based data fabric for achieving throughput of 13.3 Mpackets/s from the column to the EoC. By combining Monte Carlo physics data with high-level simulations, it has been demonstrated that the architecture meets requirements of the $VELO$ (260 Mpackets/s/$cm^2$ with efficiency of 99%).