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Pilot System for the Phase 1 Pixel Upgrade

The CMS phase 1 pixel upgrade is planned for installation in 2016-2017, incorporating new front-end ASICs with digital 400 Mbps data links to handle a higher instantaneous luminosity of up to 2.5 $x$ 10$^{34}$ cm$^{-2}$ s$^{-1}$ and trigger rates of 100 kHz with bunch spacing scenarios of 25 or 50 n...

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Detalles Bibliográficos
Autor principal: Akgun, Bora
Lenguaje:eng
Publicado: 2015
Materias:
Acceso en línea:http://cds.cern.ch/record/2049174
Descripción
Sumario:The CMS phase 1 pixel upgrade is planned for installation in 2016-2017, incorporating new front-end ASICs with digital 400 Mbps data links to handle a higher instantaneous luminosity of up to 2.5 $x$ 10$^{34}$ cm$^{-2}$ s$^{-1}$ and trigger rates of 100 kHz with bunch spacing scenarios of 25 or 50 ns. The new digital readout requires new back-end electronics incorporating faster optical receivers and firmware for decoding the new data format. Additionally the phase 1 upgrade is powered from DC-DC converters installed inside CMS close to the modules. To gain experience with this new readout chain and DC-DC converters under realistic operating conditions (trigger rates, backgrounds, high data occupancy, and possible single-event upsets) a pilot detector system comprising eight sensor modules, service electronics, optical links, and back-end electronics has been prepared using pre-production parts. The pilot system was installed with the present forward pixel detector in 2014 during long shutdown 1 (LS1). The pilot system will be operated concurrently with the present pixel detector in 2015-2016 to validate the data acquisition and powering design and advance online control system development for a rapid deployment of the full detector in 2017. This contribution will report on the phase 1 pilot system experience leading into Run 2 of the LHC.