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Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector

We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate. Tests show that the serializer is capable of running at least a...

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Detalles Bibliográficos
Autores principales: Wang, Jinhong, Guan, Liang, Sang, Ziru, Chapman, J.W., Dai, Tiesheng, Zhou, Bing, Zhu, Junjie
Lenguaje:eng
Publicado: 2015
Materias:
Acceso en línea:https://dx.doi.org/10.1109/TNS.2015.2480855
http://cds.cern.ch/record/2054710
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author Wang, Jinhong
Guan, Liang
Sang, Ziru
Chapman, J.W.
Dai, Tiesheng
Zhou, Bing
Zhu, Junjie
author_facet Wang, Jinhong
Guan, Liang
Sang, Ziru
Chapman, J.W.
Dai, Tiesheng
Zhou, Bing
Zhu, Junjie
author_sort Wang, Jinhong
collection CERN
description We report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate. Tests show that the serializer is capable of running at least at 5.76 Gbps with a bit error ratio below 1x10^{-15}, and a power consumption of 200 mW running at 4.8 Gbps. The latency between the start of loading 30 bits into the serializer to the transmission of the first bit from the serializer is measured to be about 6 ns.
id cern-2054710
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
record_format invenio
spelling cern-20547102021-05-03T20:29:50Zdoi:10.1109/TNS.2015.2480855http://cds.cern.ch/record/2054710engWang, JinhongGuan, LiangSang, ZiruChapman, J.W.Dai, TieshengZhou, BingZhu, JunjieCharacterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detectorDetectors and Experimental TechniquesWe report on the design of a serializer ASIC to be used in the ATLAS forward muon detector for trigger data transmission. We discuss the performance of a prototype chip covering power dissipation, latency and stable operating line rate. Tests show that the serializer is capable of running at least at 5.76 Gbps with a bit error ratio below 1x10^{-15}, and a power consumption of 200 mW running at 4.8 Gbps. The latency between the start of loading 30 bits into the serializer to the transmission of the first bit from the serializer is measured to be about 6 ns.arXiv:1509.06636oai:cds.cern.ch:20547102015-09-20
spellingShingle Detectors and Experimental Techniques
Wang, Jinhong
Guan, Liang
Sang, Ziru
Chapman, J.W.
Dai, Tiesheng
Zhou, Bing
Zhu, Junjie
Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector
title Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector
title_full Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector
title_fullStr Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector
title_full_unstemmed Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector
title_short Characterization of a Serializer ASIC chip for the upgrade of the ATLAS muon detector
title_sort characterization of a serializer asic chip for the upgrade of the atlas muon detector
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1109/TNS.2015.2480855
http://cds.cern.ch/record/2054710
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AT guanliang characterizationofaserializerasicchipfortheupgradeoftheatlasmuondetector
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AT chapmanjw characterizationofaserializerasicchipfortheupgradeoftheatlasmuondetector
AT daitiesheng characterizationofaserializerasicchipfortheupgradeoftheatlasmuondetector
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