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A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readout

This paper presents a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy allows also a digital background calibration, based on a code density analysis, to compensate the capacitors mismatching effects. Th...

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Detalles Bibliográficos
Autores principales: Zeloufi, Mohamed, Dzahini, Daniel, Rarbi, Fatah-ellah
Lenguaje:eng
Publicado: 2015
Materias:
Acceso en línea:http://cds.cern.ch/record/2055624
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author Zeloufi, Mohamed
Dzahini, Daniel
Rarbi, Fatah-ellah
author_facet Zeloufi, Mohamed
Dzahini, Daniel
Rarbi, Fatah-ellah
author_sort Zeloufi, Mohamed
collection CERN
description This paper presents a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy allows also a digital background calibration, based on a code density analysis, to compensate the capacitors mismatching effects. The total of capacitors used in this architecture is limited to a half of the one in a classical SAR design. Only 211 unit capacitors were necessary to reach 12bit resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12-bit 40MS/s in a CMOS 130nm 1P8M process.
id cern-2055624
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
record_format invenio
spelling cern-20556242019-09-30T06:29:59Zhttp://cds.cern.ch/record/2055624engZeloufi, MohamedDzahini, DanielRarbi, Fatah-ellahA 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readoutParticle Physics - ExperimentThis paper presents a SAR ADC with a generalized redundant search algorithm offering the flexibility to relax the requirements on the DAC settling time. The redundancy allows also a digital background calibration, based on a code density analysis, to compensate the capacitors mismatching effects. The total of capacitors used in this architecture is limited to a half of the one in a classical SAR design. Only 211 unit capacitors were necessary to reach 12bit resolution, and the switching algorithm is intrinsically monotonic. The design is fully differential featuring 12-bit 40MS/s in a CMOS 130nm 1P8M process.ATL-LARG-SLIDE-2015-741oai:cds.cern.ch:20556242015-09-28
spellingShingle Particle Physics - Experiment
Zeloufi, Mohamed
Dzahini, Daniel
Rarbi, Fatah-ellah
A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readout
title A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readout
title_full A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readout
title_fullStr A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readout
title_full_unstemmed A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readout
title_short A 12bits 40MSPS SAR ADC with a redundancy algorithm and digital calibration for the ATLAS LArg calorimeter readout
title_sort 12bits 40msps sar adc with a redundancy algorithm and digital calibration for the atlas larg calorimeter readout
topic Particle Physics - Experiment
url http://cds.cern.ch/record/2055624
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