The Phase-locked loop Algorithm of the Function Generation Controller

This paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the algorithm provides less than 10 _s of time precision and 0.5 _s of clock jitter for the WorldFIP case, and less than 2.5 _s of time precision and 40 ns of clock jitter for the Ethernet case.