The Phase-locked loop Algorithm of the Function Generation Controller

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This paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the al...

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Detalles Bibliográficos
Autores principales: Magrans De Abril, Marc, Murillo Garcia, Raul, King, Quentin
Lenguaje:eng
Publicado: 2015
Materias:
Engineering
Acceso en línea:http://cds.cern.ch/record/2064389
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author Magrans De Abril, Marc
Murillo Garcia, Raul
King, Quentin
author_facet Magrans De Abril, Marc
Murillo Garcia, Raul
King, Quentin
author_sort Magrans De Abril, Marc
collection CERN
description This paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the algorithm provides less than 10 _s of time precision and 0.5 _s of clock jitter for the WorldFIP case, and less than 2.5 _s of time precision and 40 ns of clock jitter for the Ethernet case.
id cern-2064389
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
record_format invenio
spelling cern-20643892019-09-30T06:29:59Zhttp://cds.cern.ch/record/2064389engMagrans De Abril, MarcMurillo Garcia, RaulKing, QuentinThe Phase-locked loop Algorithm of the Function Generation ControllerEngineeringThis paper describes the phase-locked loop algorithms that are used by the real-time power converter controllers at CERN. The algorithms allow the recovery of the machine time and events received by an embedded controller through WorldFIP or Ethernet-based fieldbuses. During normal operation, the algorithm provides less than 10 _s of time precision and 0.5 _s of clock jitter for the WorldFIP case, and less than 2.5 _s of time precision and 40 ns of clock jitter for the Ethernet case.CERN-ACC-2015-0136oai:cds.cern.ch:20643892015-11-03
spellingShingle Engineering
Magrans De Abril, Marc
Murillo Garcia, Raul
King, Quentin
The Phase-locked loop Algorithm of the Function Generation Controller
title The Phase-locked loop Algorithm of the Function Generation Controller
title_full The Phase-locked loop Algorithm of the Function Generation Controller
title_fullStr The Phase-locked loop Algorithm of the Function Generation Controller
title_full_unstemmed The Phase-locked loop Algorithm of the Function Generation Controller
title_short The Phase-locked loop Algorithm of the Function Generation Controller
title_sort phase-locked loop algorithm of the function generation controller
topic Engineering
url http://cds.cern.ch/record/2064389
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