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Analysis and design of networks-on-chip under high process variation
This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconn...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
Springer
2015
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1007/978-3-319-25766-2 http://cds.cern.ch/record/2120203 |