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A low power high speed radiation hard serializer for High Energy Physics experiments

This Ph.D. thesis focuses on the development and the characterization of novel solutions for electronic systems for high-speed data transmission in extremely high radio-active environment (e.g. high energy physics application). The text proposes two alternative full-custom solutions for a fundamenta...

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Autor principal: Felici, Daniele
Lenguaje:eng
Publicado: 2016
Materias:
Acceso en línea:http://cds.cern.ch/record/2146021
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author Felici, Daniele
author_facet Felici, Daniele
author_sort Felici, Daniele
collection CERN
description This Ph.D. thesis focuses on the development and the characterization of novel solutions for electronic systems for high-speed data transmission in extremely high radio-active environment (e.g. high energy physics application). The text proposes two alternative full-custom solutions for a fundamental enabling block for a lowpower serial data transmission system, the serializer. This block will find place in a future transceiver conceived for the future upgraded phase of the Large Hadron Collider, or LHC, at CERN. The first solution proposed, called “triple module redundancy”, is based on hardware redundancy, a well-known solution, to obtain protection against the temporary malfunctioning induced by radiation. In the second case a new architecture, called “code protected”, is proposed. This architecture takes advantage of the error correction code present in the data word to obtain radiation robustness on data and some parts of the control logic and to further reduce the power consumption. A test chip has been designed and implemented in a 65-nm commercial CMOS technology chosen by CERN scientific community to be used in several new electronics blocks developed for the future phase of the LHC. The designed chip has been used to validate and characterized the serializers. The test results show that the two blocks match the requirements. In fact, the two proposed blocks can guarantee an average power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. In addition, both blocks can work continuously for a period of 10 years in the CERN LHC radio-active environment (100 Mrad of total dose is expected within this period) guaranteeing an error rate smaller than 1 error per day. A deep analysis and optimization of the basic gates (flip flops, combinatorial gates, etc.) performances has been required, since the technology chosen has never been used before for this kind of application. In particular, a new radiation robust flip flop, called “F-Dice”, has been developed and characterized on silicon. These studies are also presented in the text.
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institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2016
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spelling cern-21460212019-09-30T06:29:59Zhttp://cds.cern.ch/record/2146021engFelici, DanieleA low power high speed radiation hard serializer for High Energy Physics experimentsEngineeringThis Ph.D. thesis focuses on the development and the characterization of novel solutions for electronic systems for high-speed data transmission in extremely high radio-active environment (e.g. high energy physics application). The text proposes two alternative full-custom solutions for a fundamental enabling block for a lowpower serial data transmission system, the serializer. This block will find place in a future transceiver conceived for the future upgraded phase of the Large Hadron Collider, or LHC, at CERN. The first solution proposed, called “triple module redundancy”, is based on hardware redundancy, a well-known solution, to obtain protection against the temporary malfunctioning induced by radiation. In the second case a new architecture, called “code protected”, is proposed. This architecture takes advantage of the error correction code present in the data word to obtain radiation robustness on data and some parts of the control logic and to further reduce the power consumption. A test chip has been designed and implemented in a 65-nm commercial CMOS technology chosen by CERN scientific community to be used in several new electronics blocks developed for the future phase of the LHC. The designed chip has been used to validate and characterized the serializers. The test results show that the two blocks match the requirements. In fact, the two proposed blocks can guarantee an average power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. In addition, both blocks can work continuously for a period of 10 years in the CERN LHC radio-active environment (100 Mrad of total dose is expected within this period) guaranteeing an error rate smaller than 1 error per day. A deep analysis and optimization of the basic gates (flip flops, combinatorial gates, etc.) performances has been required, since the technology chosen has never been used before for this kind of application. In particular, a new radiation robust flip flop, called “F-Dice”, has been developed and characterized on silicon. These studies are also presented in the text.CERN-THESIS-2015-323oai:cds.cern.ch:21460212016-04-14T10:21:16Z
spellingShingle Engineering
Felici, Daniele
A low power high speed radiation hard serializer for High Energy Physics experiments
title A low power high speed radiation hard serializer for High Energy Physics experiments
title_full A low power high speed radiation hard serializer for High Energy Physics experiments
title_fullStr A low power high speed radiation hard serializer for High Energy Physics experiments
title_full_unstemmed A low power high speed radiation hard serializer for High Energy Physics experiments
title_short A low power high speed radiation hard serializer for High Energy Physics experiments
title_sort low power high speed radiation hard serializer for high energy physics experiments
topic Engineering
url http://cds.cern.ch/record/2146021
work_keys_str_mv AT felicidaniele alowpowerhighspeedradiationhardserializerforhighenergyphysicsexperiments
AT felicidaniele lowpowerhighspeedradiationhardserializerforhighenergyphysicsexperiments