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Electronics Design and Layout Complexity of the ATLAS New Small Wheels

The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will allow to increase the luminosity to 2×1034 cm−2s−1 and 5×1034 cm−2s−1, respectively. For the ultimate HL-LHC phase the expected mean number of interactions per bunch crossing will increase from 55 at 2×1034 cm−2s−1 t...

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Detalles Bibliográficos
Autor principal: Moschovakos, Paris
Lenguaje:eng
Publicado: 2016
Materias:
Acceso en línea:http://cds.cern.ch/record/2196939
Descripción
Sumario:The upgrades of the LHC accelerator and the experiments in 2019/20 and 2023/24 will allow to increase the luminosity to 2×1034 cm−2s−1 and 5×1034 cm−2s−1, respectively. For the ultimate HL-LHC phase the expected mean number of interactions per bunch crossing will increase from 55 at 2×1034 cm−2s−1 to ∼140 at 5×1034 cm−2s−1. This increase, drastically impacts the ATLAS trigger and trigger rates. For the ATLAS Muon Spectrometer, a replacement of the innermost endcap stations, the so called “Small Wheels” operating in a magnetic field, is therefore planned for 2019/20 to be able to maintain a low pT threshold for single muon and excellent tracking capability in the HL-LHC regime. The New Small Wheels will feature two new detector technologies, Resistive Micromegas and small strip Thin Gap Chambers conforming a system of ~2.4 million readout channels. Both detector technologies will provide trigger and tracking primitives fully compliant with the post-2024 HL-LHC operation. To allow for some safety margin, the design studies assume a maximum instantaneous luminosity of 7×1034 cm−2 s−1, 200 pile-up events, trigger rates of 1 MHz at Level-0 and 400 KHz at Level-1. A radiation dose of ~ 1700 Gy (inner radius) is expected. The electronics design of such a system will be implemented in some 8000 front-end boards including the design of 4 different custom front-end ASICs. Among them the 64 channels VMM, a common frontend ASIC for both detector technologies and charge-interpolating trackers, providing amplitude, timing measurements, per channel analog-to-digital conversions and in parallel direct trigger outputs. The candidate selection is designed within the budget latency of 1 us, and 6 us after 2024. Moreover, the design integrates the GBTx (Gigabit transceiver) ASIC and a Slow Control ASIC developed at CERN. The data flow is designed through a high-throughput network approach. The overall design will be presented.