Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. The developed firmware includes the logical blocks required for the transmission of a BPM encoded data stream to the detector, reception and decoding of the 8b10b data stream from the detector, as well as communication to and control of these logical blocks. The firmware is tested on a commercial FPGA evaluation platform and is able to operate in a standalone manner controlled by a PC. The basic functionalities of the IBL-BOC firmware are demonstrated and tested with this setup. An exemplary readout of the new IBL detector hardware further proves the versatile design of the firmware.