Evaluation of radiation tolerance of TMR designs in SRAM-based FPGA.

During the Summer Student program in CERN I was working in the CMS Muon Drift Tube group, building a setup for evaluating the radiation tolerance of the drift tube signal encoding hardware (Time-to-Digital Converter, TDC) implemented in SRAM-based FPGA using Triple Modular Redundancy (TMR). While commercially available SRAM-based FPGAs have more computational power, are more advanced in general than flash-based FPGAs and are the most suitable technology for implementing the TDC logic (also taking into account the performance requirements), in the context of operation inside an environment with high levels of ionizing radiation (such as inside CMS DT detector) they are more susceptible to configuration memory bit flips – Single Event Upsets (SEUs) - due to lower required energy for a memory bit being flipped. The effect of a SEU inside the configuration memory might change the functionality of the underlying building blocks of FPGA and if the respective blocks were involved in implementing the desired custom hardware logic, the latter may also change. This may result in an erroneous operation or complete stopping of the TDC and hence render it useless for intended purposes. To restore the normal operation, FPGA normally has to be reconfigured. In order to avoid reconfiguring the FPGA in case of an SEU while still keeping using SRAM-based FPGA because of their high performance, a different approach can be taken to make the logic tolerant to SEU in the configuration memory by using the TMR approach – essentially triplicating the functional logic and then detecting and masking the occurring errors in one of the copies. During the 9-week period of the Summer Student project my task was to implement the TMR for the TDC circuit and test it by performing an error injection campaign.