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Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.

First, a hardware design is created using Qsys in Quartus 16.0. Creation of the hardware design consists of configuring Hard Processor System (HPS) inside FPGA and adding necessary hardware blocks to the design. After generating the Qsys design, it is then instantiated in top level module in Verilog...

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Autor principal: Zahid Rasheed, Awais
Lenguaje:eng
Publicado: 2016
Materias:
Acceso en línea:http://cds.cern.ch/record/2214525
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author Zahid Rasheed, Awais
author_facet Zahid Rasheed, Awais
author_sort Zahid Rasheed, Awais
collection CERN
description First, a hardware design is created using Qsys in Quartus 16.0. Creation of the hardware design consists of configuring Hard Processor System (HPS) inside FPGA and adding necessary hardware blocks to the design. After generating the Qsys design, it is then instantiated in top level module in Verilog or VHDL. After setting up all pin assignments and adding all necessary files in the design, project is compiled to have a complete hardware design. Second part comprises full software design in correspondence with the hardware design and booting the HPS from SD card. Software includes enabling the different bridges used by HPS to communicate with FPGA, configuring FPGA from HPS and embedded application itself. Finally, everything is added in the SD card to get a complete automatic bare metal application running on the host board without any configuration what so ever.
id cern-2214525
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2016
record_format invenio
spelling cern-22145252019-09-30T06:29:59Zhttp://cds.cern.ch/record/2214525engZahid Rasheed, AwaisConfiguration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.Computing and ComputersEngineeringFirst, a hardware design is created using Qsys in Quartus 16.0. Creation of the hardware design consists of configuring Hard Processor System (HPS) inside FPGA and adding necessary hardware blocks to the design. After generating the Qsys design, it is then instantiated in top level module in Verilog or VHDL. After setting up all pin assignments and adding all necessary files in the design, project is compiled to have a complete hardware design. Second part comprises full software design in correspondence with the hardware design and booting the HPS from SD card. Software includes enabling the different bridges used by HPS to communicate with FPGA, configuring FPGA from HPS and embedded application itself. Finally, everything is added in the SD card to get a complete automatic bare metal application running on the host board without any configuration what so ever.CERN-STUDENTS-Note-2016-193oai:cds.cern.ch:22145252016-09-07
spellingShingle Computing and Computers
Engineering
Zahid Rasheed, Awais
Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.
title Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.
title_full Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.
title_fullStr Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.
title_full_unstemmed Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.
title_short Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.
title_sort configuration of soc fpga, booting of hps and running bare metal application from sd card.
topic Computing and Computers
Engineering
url http://cds.cern.ch/record/2214525
work_keys_str_mv AT zahidrasheedawais configurationofsocfpgabootingofhpsandrunningbaremetalapplicationfromsdcard