Cargando…
Configuration of SoC FPGA, Booting of HPS and running Bare Metal Application from SD card.
First, a hardware design is created using Qsys in Quartus 16.0. Creation of the hardware design consists of configuring Hard Processor System (HPS) inside FPGA and adding necessary hardware blocks to the design. After generating the Qsys design, it is then instantiated in top level module in Verilog...
| Autor principal: | |
|---|---|
| Lenguaje: | eng |
| Publicado: |
2016
|
| Materias: | |
| Acceso en línea: | http://cds.cern.ch/record/2214525 |