Module and electronics developments for the ATLAS ITK pixel system

Summary ATLAS is preparing for an extensive modification of its detector in the course of the planned HL‐ LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all‐silicon detector (Inner Tracker, ITk). A revised trigger and data taking system is foreseen with triggers expected at lowest level at an average rate of 1 MHz. The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL‐LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in early 2017. A new on‐detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on‐going R&D within the ATLAS ITK project towards the new pixel modules and the off‐detector electronics. Planar and 3D sensors are being re‐designed with cell sizes of 50x50 or 25x100 μm2, compatible with the RD53 chip. A sensor thickness equal or less than 150‐200 μm is foreseen for the outer layers, where high yield and low costs are required, and 100‐150 μm in the two innermost ones where radiation hardness is the major concern. Several prototyping sensor productions are being carried out at the moment in collaboration with commercial vendors to identify the best technology for the different pixel layers. A particularly challenging aspect of the ITK pixel module assembly is represented by the sensor‐ chip interconnection given the large area to be covered and the compressed production schedule. Multiple industrial suppliers are being qualified with FE‐I4 multi‐chip modules but the procedure will have to be reiterated with the final ITK read‐out chip due to the higher bump density and the larger chip wafer size (12” for the 65 nm CMOS technology versus the 8” of the 130 nm CMOS). An intense R&D is being carried out to satisfy the yield requirements when using 100‐150 μm thin chips and towards cost reduction, exploring the feasibility of mask‐less UBM or wafer to wafer interconnection. A possible solution would be the implementation of monolithic HV or HR CMOS sensors, also being actively studied. A specific R&D program has been started with the aim of producing and testing large size (1‐2 cm2) demonstrators of this technology by the end of 2016. CMOS sensors, potentially offering a significant cost reduction with respect to traditional hybrid pixel detectors, could be particularly interesting for the outermost pixel layers. The pixel off detector read‐out electronics will be implemented in the framework of the general ATLAS trigger and DAQ system. It will consist of firmware‐based components on the receiving end of the FE electronics, a distribution system for timing, trigger and command and a data handling part connected via a commodity multi‐gigabit network. The same system is used to calibrate the detector modules during operation to adjust for radiation‐induced changes in sensors and electronics. Reading out the module data especially for the innermost layer, in which the hit occupancy is the highest, a readout system serving a data rate of several Gb/s is under development. Simulations based on the expected hit rates and the foreseen performance of the RD53 chip indicate that a readout speed of up to 5 Gb/s per data link (FE‐chip) is necessary in the innermost layers going down to 640 Mb/s for the outermost. Because of the very high radiation level inside the detector, the first part of transmission has to be implemented electrically with signals to be converted for optical transmission at larger radii. For this reason cables are being developed for electrical data transmission at rates of up to 5 Gb/s over several metres. To save material in the servicing cables, serial powering is the baseline option for the ITK pixel system and extensive tests are being carried out with FE‐I4 modules thanks to the dedicated shunt‐regulators (Shunt‐LDO) implemented in the IBL chip that can be operated with a constant current as needed for serial powering. Not to lose a whole chain in case of a single module failing, a special protection chip to be placed on the module flex is being developed to switch on/off individual modules.