Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the whole chain is measured to be around 7 fC in its nominal frequency band width.