The Development of High-Performance Front-End Electronics Based Upon the QIE12 Custom ASIC for the ATLAS TileCal Upgrade

We present the design of a new candidate front-end electronic readout system being developed for the ATLAS TileCal Phase 2 Upgrade. The system is based upon the QIE12 custom Application Specific Integrated Circuit. The chip features a least count sensitivity of 1.5 fC, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. The design incorporates an on-board current integrator, and has several calibration systems. The new electronics will operate dead-timelessly at 40 MHz, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room using high-speed optical links. The system is one of three candidate systems for the Phase 2 Upgrade. We have built a “Demonstrator” – a fully functional prototype of the new system. Performance results from bench measurements and from a recent test beam campaign will be presented.