Cargando…
Simulation Environment Based on the Universal Verification Methodology
Universal Verification Methodology (UVM) is a standardized approach of verifying integrated circuit designs, targeting a Coverage-Driven Verification (CDV). It combines automatic test generation, self-checking testbenches, and coverage metrics to indicate progress in the design verification. The flo...
| Autor principal: | |
|---|---|
| Lenguaje: | eng |
| Publicado: |
2017
|
| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/12/01/C01001 http://cds.cern.ch/record/2232660 |