FPGA-based algorithms for the new trigger system for the phase 2 Upgrade of the CMS Drift Tubes detector

The Phase 2 upgrade of the CMS Drift Tubes detector aims at moving all the readout and trigger electronics from the inner detector to outside the cavern. Trigger algorithms need to be redesigned to handle direct timing information and remove present bottlenecks of resolution and deadtime, approaching to present high level trigger performance. In the present contribution we describe the work that has been performed to emulate the firmware that process 1 ns TDC hits from one DT chamber with the combinatorial problematic of the arrival time uncertainty in a detector with up to 400 ns of drift time.