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FTK: The hardware Fast TracKer of the ATLAS experiment at CERN
In the ever increasing pile-up of the Large Hadron Collider environment the trigger systems of the experiments have to be exceedingly sophisticated and fast at the same time in order to increase the rate of relevant physics processes with respect to background processes. The Fast TracKer (FTK) is a...
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Lenguaje: | eng |
Publicado: |
2016
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1051/epjconf/201713712001 http://cds.cern.ch/record/2233653 |
Sumario: | In the ever increasing pile-up of the Large Hadron Collider environment the trigger systems of the experiments have to be exceedingly sophisticated and fast at the same time in order to increase the rate of relevant physics processes with respect to background processes. The Fast TracKer (FTK) is a track finding implementation at hardware level that is designed to deliver full-scan tracks with $p_{T}$ above 1GeV to the ATLAS trigger system for every L1 accept (at a maximum rate of 100kHz). To accomplish this, FTK is a highly parallel system which is currently under installation in ATLAS. It will first provide the trigger system with tracks in the central region of the ATLAS detector, and next year it is expected that it will cover the whole detector. The system is based on pattern matching between hits coming from the silicon trackers of the ATLAS detector and 1 billion simulated patterns stored in specially designed ASIC chips (Associative Memory – AM06). In a first stage, coarse resolution hits are matched against the patterns and the accepted hits undergo track fitting implemented at FPGA level. Tracks above the 1GeV threshold are delivered to the High Level Trigger within about 100$\mu$s. The resolution of the tracks coming from FTK is close to the offline tracking resolution allowing reliable detection of primary and secondary vertices at trigger level and an improved trigger performance for $b$-jets and $\tau$ leptons. This document will provide an overview of the FTK system architecture, its design and information about its expected performance. |
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