Cargando…
Designing with Xilinx FPGAs: using Vivado
| Autor principal: | |
|---|---|
| Lenguaje: | eng |
| Publicado: |
Springer
2016
|
| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1007/978-3-319-42438-5 http://cds.cern.ch/record/2237939 |
| _version_ | 1780952882971934720 |
|---|---|
| author | Churiwala, Sanjay |
| author_facet | Churiwala, Sanjay |
| author_sort | Churiwala, Sanjay |
| collection | CERN |
| id | cern-2237939 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2016 |
| publisher | Springer |
| record_format | invenio |
| spelling | cern-22379392021-04-21T19:25:36Zdoi:10.1007/978-3-319-42438-5http://cds.cern.ch/record/2237939engChuriwala, SanjayDesigning with Xilinx FPGAs: using VivadoEngineeringSpringeroai:cds.cern.ch:22379392016 |
| spellingShingle | Engineering Churiwala, Sanjay Designing with Xilinx FPGAs: using Vivado |
| title | Designing with Xilinx FPGAs: using Vivado |
| title_full | Designing with Xilinx FPGAs: using Vivado |
| title_fullStr | Designing with Xilinx FPGAs: using Vivado |
| title_full_unstemmed | Designing with Xilinx FPGAs: using Vivado |
| title_short | Designing with Xilinx FPGAs: using Vivado |
| title_sort | designing with xilinx fpgas: using vivado |
| topic | Engineering |
| url | https://dx.doi.org/10.1007/978-3-319-42438-5 http://cds.cern.ch/record/2237939 |
| work_keys_str_mv | AT churiwalasanjay designingwithxilinxfpgasusingvivado |