Module and Electronics Developments for the ATLAS ITK Pixel System

ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m$^{2}$, depending on the final layout choice that is expected to take place in early 2017. An intense R\&D activity is taking place in the field of planar, 3D, CMOS sensors to identify the optimal technology for the different pixel layers. In parallel various sensor-chip interconnection options are explored to identify reliable technologies when employing 100-150~$\mu$m thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off detector read-out electronics will be implemented in the framework of the general ATLAS trigger and DAQ system. Simulations indicate that a readout speed of up to 5 Gb/s per data link (FE-chip) is necessary in the innermost layers going down to 640 Mb/s for the outermost. Because of the very high radiation level inside the detector, the first part of transmission has to be implemented electrically with signals to be converted for optical transmission at larger radii. Extensive tests are being carried out to prove the feasibility of implementing serial powering chosen as the baseline for the ITK pixel system, given the reduced material in the servicing cables foreseen for this option.