Cargando…
Formal verification of Simulink/Stateflow diagrams: a deductive approach
This book presents a state-of-the-art technique for formal verification of continuous-time Simulink/Stateflow diagrams, featuring an expressive hybrid system modelling language, a powerful specification logic and deduction-based verification approach, and some impressive, realistic case studies. Rea...
Autores principales: | Zhan, Naijun, Wang, Shuling, Zhao, Hengjun |
---|---|
Lenguaje: | eng |
Publicado: |
Springer
2017
|
Materias: | |
Acceso en línea: | https://dx.doi.org/10.1007/978-3-319-47016-0 http://cds.cern.ch/record/2240467 |
Ejemplares similares
-
Digital integrated circuits: design-for-test using Simulink and Stateflow
por: Perelroyzen, Evgeni
Publicado: (2006) -
Matlab - Simulink - Stateflow : grundlagen, toolboxen, beispiele
Publicado: (2002) -
Signals and systems with MATLAB and Simulink modeling
por: Karis, Steven, T
Publicado: (2008) -
Hardware design verification: simulation and formal method-based approaches
por: Lam, William K C
Publicado: (2005) -
Modeling of digital communication systems using SIMULINK
por: Giordano, Arthur A, et al.
Publicado: (2015)