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Hardware IP security and trust
This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the sec...
Autores principales: | , , |
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Lenguaje: | eng |
Publicado: |
Springer
2017
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1007/978-3-319-49025-0 http://cds.cern.ch/record/2243798 |
_version_ | 1780953328650289152 |
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author | Mishra, Prabhat Bhunia, Swarup Tehranipoor, Mark |
author_facet | Mishra, Prabhat Bhunia, Swarup Tehranipoor, Mark |
author_sort | Mishra, Prabhat |
collection | CERN |
description | This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs. |
id | cern-2243798 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2017 |
publisher | Springer |
record_format | invenio |
spelling | cern-22437982021-04-21T19:21:41Zdoi:10.1007/978-3-319-49025-0http://cds.cern.ch/record/2243798engMishra, PrabhatBhunia, SwarupTehranipoor, MarkHardware IP security and trustEngineeringThis book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.Springeroai:cds.cern.ch:22437982017 |
spellingShingle | Engineering Mishra, Prabhat Bhunia, Swarup Tehranipoor, Mark Hardware IP security and trust |
title | Hardware IP security and trust |
title_full | Hardware IP security and trust |
title_fullStr | Hardware IP security and trust |
title_full_unstemmed | Hardware IP security and trust |
title_short | Hardware IP security and trust |
title_sort | hardware ip security and trust |
topic | Engineering |
url | https://dx.doi.org/10.1007/978-3-319-49025-0 http://cds.cern.ch/record/2243798 |
work_keys_str_mv | AT mishraprabhat hardwareipsecurityandtrust AT bhuniaswarup hardwareipsecurityandtrust AT tehranipoormark hardwareipsecurityandtrust |