Analysis and simulation of HV-CMOS assemblies for the CLIC vertex detector

One of the design concepts currently under study for the vertex detector at the proposed Compact Linear Collider is a High-Voltage CMOS sensor, fabricated in a commercial 180 nm technology, capacitively coupled to a hybrid readout chip. Tests of the assemblies were carried out at the CERN SPS using 120 GeV/c pions, covering incident angles ranging from 0$^\circ$ to 80$^\circ$. The measurements have shown an excellent tracking performance with an efficiency above 99.7% and a spatial resolution of 5–7 $\mu$m over the tested angular range. These results were then compared to TCAD simulations carried out using simulations, showing a good agreement for the current-voltage, breakdown and charge collection properties. The simulations have also been used to optimise future sensor design.