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System reduction for nanoscale IC design

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design...

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Detalles Bibliográficos
Autor principal: Benner, Peter
Lenguaje:eng
Publicado: Springer 2017
Materias:
Acceso en línea:https://dx.doi.org/10.1007/978-3-319-07236-4
http://cds.cern.ch/record/2272822
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author Benner, Peter
author_facet Benner, Peter
author_sort Benner, Peter
collection CERN
description This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.
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spelling cern-22728222021-04-21T19:09:16Zdoi:10.1007/978-3-319-07236-4http://cds.cern.ch/record/2272822engBenner, PeterSystem reduction for nanoscale IC designMathematical Physics and MathematicsThis book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics.Springeroai:cds.cern.ch:22728222017
spellingShingle Mathematical Physics and Mathematics
Benner, Peter
System reduction for nanoscale IC design
title System reduction for nanoscale IC design
title_full System reduction for nanoscale IC design
title_fullStr System reduction for nanoscale IC design
title_full_unstemmed System reduction for nanoscale IC design
title_short System reduction for nanoscale IC design
title_sort system reduction for nanoscale ic design
topic Mathematical Physics and Mathematics
url https://dx.doi.org/10.1007/978-3-319-07236-4
http://cds.cern.ch/record/2272822
work_keys_str_mv AT bennerpeter systemreductionfornanoscaleicdesign