Phase correction on FPGA for TOTEM clock distribution system

A phase correction module has been implemented on FPGA, to control the delay of the clock at TOTEM timing detectors. The module consists of two parts: a phase shifter and a phase detector. The design of the phase shifter has been completed and was tested in the laboratory. The output jitter was measured and met the requirements. The phase detector design has also been completed and tested with a behavioural simulation, which outlined some weaknesses due to intrinsic limitations of FPGAs. The obtained resolution, although below ns scale, could not satisfy the requirements. A discussion on how to improve the performance of the phase detector is included.