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Phase correction on FPGA for TOTEM clock distribution system

A phase correction module has been implemented on FPGA, to control the delay of the clock at TOTEM timing detectors. The module consists of two parts: a phase shifter and a phase detector. The design of the phase shifter has been completed and was tested in the laboratory. The output jitter was meas...

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Autor principal: Bellina, Alessandra
Lenguaje:eng
Publicado: 2017
Materias:
Acceso en línea:http://cds.cern.ch/record/2280911
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author Bellina, Alessandra
author_facet Bellina, Alessandra
author_sort Bellina, Alessandra
collection CERN
description A phase correction module has been implemented on FPGA, to control the delay of the clock at TOTEM timing detectors. The module consists of two parts: a phase shifter and a phase detector. The design of the phase shifter has been completed and was tested in the laboratory. The output jitter was measured and met the requirements. The phase detector design has also been completed and tested with a behavioural simulation, which outlined some weaknesses due to intrinsic limitations of FPGAs. The obtained resolution, although below ns scale, could not satisfy the requirements. A discussion on how to improve the performance of the phase detector is included.
id cern-2280911
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2017
record_format invenio
spelling cern-22809112019-09-30T06:29:59Zhttp://cds.cern.ch/record/2280911engBellina, AlessandraPhase correction on FPGA for TOTEM clock distribution systemEngineeringA phase correction module has been implemented on FPGA, to control the delay of the clock at TOTEM timing detectors. The module consists of two parts: a phase shifter and a phase detector. The design of the phase shifter has been completed and was tested in the laboratory. The output jitter was measured and met the requirements. The phase detector design has also been completed and tested with a behavioural simulation, which outlined some weaknesses due to intrinsic limitations of FPGAs. The obtained resolution, although below ns scale, could not satisfy the requirements. A discussion on how to improve the performance of the phase detector is included.CERN-STUDENTS-Note-2017-108oai:cds.cern.ch:22809112017-08-25
spellingShingle Engineering
Bellina, Alessandra
Phase correction on FPGA for TOTEM clock distribution system
title Phase correction on FPGA for TOTEM clock distribution system
title_full Phase correction on FPGA for TOTEM clock distribution system
title_fullStr Phase correction on FPGA for TOTEM clock distribution system
title_full_unstemmed Phase correction on FPGA for TOTEM clock distribution system
title_short Phase correction on FPGA for TOTEM clock distribution system
title_sort phase correction on fpga for totem clock distribution system
topic Engineering
url http://cds.cern.ch/record/2280911
work_keys_str_mv AT bellinaalessandra phasecorrectiononfpgafortotemclockdistributionsystem