Cargando…

CMOS 65nm engineering run

Detalles Bibliográficos
Autor principal:	Re, Valerio
Formato:	info:eu-repo/semantics/article
Lenguaje:	eng
Publicado:	2018
Materias:	Detectors and Experimental Techniques 4: Micro-electronics and interconnections
Acceso en línea:	http://cds.cern.ch/record/2312151

Ejemplares similares

Final design review of 65nm CMOS chips
por: Re, Valerio
Publicado: (2017)

Architectural review of deliverable chips in 65nm run
por: Re, V.
Publicado: (2016)

A front-end channel in 65 nm CMOS for pixel detectors at the HL-LHC experiment upgrades
por: Ratti, L, et al.
Publicado: (2017)

Ionizing Radiation Effects on the Noise of 65 nm CMOS Transistors for Pixel Sensor Readout at Extreme Total Dose Levels
por: Re, V., et al.
Publicado: (2018)

Final design review of deliverable D4.3 (TSV in 65nm)
por: Re, Valerio
Publicado: (2017)

Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC
por: Pacher, L., et al.
Publicado: (2018)

Test results and prospects for RD53A, a large scale 65 nm CMOS chip for pixel readout at the HL-LHC
por: Gaioni, Luigi
Publicado: (2019)

Test results of the CHIPIX65 asynchronous front-end for the HL-LHC experiment upgrades
por: Gaioni, Luigi; De Canio, Francesco; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca
Publicado: (2018)

BICMOS SiGe engineering run
por: Seguin-Moreau, N.
Publicado: (2018)

Final design review of 130nm ASICs
por: De la Taille, Christophe
Publicado: (2017)

First test results of the CHIPIX65 asynchronous front-end connected to a 3D sensor
por: Gaioni, L., et al.
Publicado: (2019)

Test report of deliverable D4.1
por: Re, Valerio
Publicado: (2019)

3D integration and silicon pixel detectors
por: Re, Valerio
Publicado: (2019)

Through silicon vias production
por: Re, Valerio
Publicado: (2019)

Test report of deliverable D4.3
por: Re, Valerio
Publicado: (2020)

Selection of TSV process
por: Re, V.
Publicado: (2016)

Perspectives of 65 nm CMOS technologies for high performance front-end electronics
por: Traversi, G, et al.
Publicado: (2014)

ALTIROC0, a 20 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)
por: de la Taille, C., et al.
Publicado: (2018)

Test report of deliverable D4.2
por: De la Taille, Christophe
Publicado: (2019)

SiPM with Nal/BGO Scintillators approach as Compton Suppressors for FIPPS
por: Ayala Fernandez, Paola
Publicado: (2017)

Selection of SiGe foundry
por: de La Taille, C.
Publicado: (2016)

65-nm CMOS front-end channel for pixel readout in the HL-LHC radiation environment
por: Ratti, Lodovico, et al.
Publicado: (2017)

Characterization of a commercial 65 nm CMOS technology for SLHC applications
por: Bonacini, S, et al.
Publicado: (2012)

Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications
por: De Canio, Francesco, et al.
Publicado: (2018)

65 nm CMOS analog front-end for pixel detectors at the HL-LHC
por: Gaioni, L, et al.
Publicado: (2016)

Pixel front-end development in 65 nm CMOS technology
por: Havránek, M, et al.
Publicado: (2014)

A 65 nm CMOS analog processor with zero dead time for future pixel detectors
por: Gaioni, L, et al.
Publicado: (2017)

Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2022)

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics
por: Rinella, G Aglieri, et al.
Publicado: (2023)

1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades
por: Menouni, M, et al.
Publicado: (2015)

Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2021)

Development of scalable frequency and power Phase-Locked Loop in 130nm CMOS technology
por: Firlej, M, et al.
Publicado: (2014)

Charge sensing properties of monolithic CMOS pixel sensors fabricated in a 65 nm technology
por: Bugiel, Szymon, et al.
Publicado: (2022)

A High-Resolution Clock Phase-Shifter in a 65 nm CMOS Technology
por: Yang, Dongxu, et al.
Publicado: (2018)

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology
por: Zeng, Zhiyao, et al.
Publicado: (2017)

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
por: Gaioni, L, et al.
Publicado: (2018)

Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS
por: Chevas, Loukas, et al.
Publicado: (2018)

Design of an analog monolithic pixel sensor prototype in TPSCo 65 nm CMOS imaging technology
por: Deng, W, et al.
Publicado: (2023)

A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC
por: Paternò, Andrea, et al.
Publicado: (2017)

Prototype of a gigabit data transmitter in 65 nm CMOS for DEPFET pixel detectors at Belle-II
por: Kishishita, T, et al.
Publicado: (2013)

Cannot write session to /tmp/vufind_sessions/sess_oer54novnjodn8sb7e27eqocq5