A 1 GHz RF Trigger Unit implemented in FPGA logic

Applications of Trigger Units (TU) can be found in almost all accelerators at CERN. The requirements in terms of operating frequencies, configuration or modes of operation change from one application to another, how-ever, in terms of design requirements for the Trigger Unit, the operating frequency...

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Detalles Bibliográficos
Autores principales: Barrientos, D., Molendijk, J., Hagmann, G.
Lenguaje:eng
Publicado: 2018
Materias:
physics.acc-ph
Accelerators and Storage Rings
Acceso en línea:http://cds.cern.ch/record/2314652
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author Barrientos, D.
Molendijk, J.
Hagmann, G.
author_facet Barrientos, D.
Molendijk, J.
Hagmann, G.
author_sort Barrientos, D.
collection CERN
description Applications of Trigger Units (TU) can be found in almost all accelerators at CERN. The requirements in terms of operating frequencies, configuration or modes of operation change from one application to another, how-ever, in terms of design requirements for the Trigger Unit, the operating frequency is probably the most demanding one. In this work, we present an implementation of a Trigger Unit almost fully embedded in the FPGA logic operating at a maximum frequency of 1 GHz using the internal serializer/deserializer circuitry to simplify the timing constraints of the design. This implementation allows easy reconfiguration of the module and the development of new modes of operation, which are described in this paper.
id cern-2314652
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2018
record_format invenio
spelling cern-23146522023-03-14T18:38:49Zhttp://cds.cern.ch/record/2314652engBarrientos, D.Molendijk, J.Hagmann, G.A 1 GHz RF Trigger Unit implemented in FPGA logicphysics.acc-phAccelerators and Storage RingsApplications of Trigger Units (TU) can be found in almost all accelerators at CERN. The requirements in terms of operating frequencies, configuration or modes of operation change from one application to another, how-ever, in terms of design requirements for the Trigger Unit, the operating frequency is probably the most demanding one. In this work, we present an implementation of a Trigger Unit almost fully embedded in the FPGA logic operating at a maximum frequency of 1 GHz using the internal serializer/deserializer circuitry to simplify the timing constraints of the design. This implementation allows easy reconfiguration of the module and the development of new modes of operation, which are described in this paper.arXiv:1803.09041LLRF2017/P-65LLRF2017-P-65oai:cds.cern.ch:23146522018
spellingShingle physics.acc-ph
Accelerators and Storage Rings
Barrientos, D.
Molendijk, J.
Hagmann, G.
A 1 GHz RF Trigger Unit implemented in FPGA logic
title A 1 GHz RF Trigger Unit implemented in FPGA logic
title_full A 1 GHz RF Trigger Unit implemented in FPGA logic
title_fullStr A 1 GHz RF Trigger Unit implemented in FPGA logic
title_full_unstemmed A 1 GHz RF Trigger Unit implemented in FPGA logic
title_short A 1 GHz RF Trigger Unit implemented in FPGA logic
title_sort 1 ghz rf trigger unit implemented in fpga logic
topic physics.acc-ph
Accelerators and Storage Rings
url http://cds.cern.ch/record/2314652
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AT molendijkj a1ghzrftriggerunitimplementedinfpgalogic
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AT barrientosd 1ghzrftriggerunitimplementedinfpgalogic
AT molendijkj 1ghzrftriggerunitimplementedinfpgalogic
AT hagmanng 1ghzrftriggerunitimplementedinfpgalogic

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