Cargando…

IV Characterisation for the VELO Upgrade

LHCb is a dedicated heavy flavour physics experiment that operates at the LHC. The LHCb collaboration plans to change key features of the present detectors for Run III, moving to a full detector readout at 40MHz and operating at a luminosity of 1-2x1033cm-2s-1. The new Vertex Locator (VELO) detecto...

Descripción completa

Detalles Bibliográficos
Autor principal: Franco Lima, Vinicius
Lenguaje:eng
Publicado: 2018
Acceso en línea:http://cds.cern.ch/record/2314659
_version_ 1780958108811526144
author Franco Lima, Vinicius
author_facet Franco Lima, Vinicius
author_sort Franco Lima, Vinicius
collection CERN
description LHCb is a dedicated heavy flavour physics experiment that operates at the LHC. The LHCb collaboration plans to change key features of the present detectors for Run III, moving to a full detector readout at 40MHz and operating at a luminosity of 1-2x1033cm-2s-1. The new Vertex Locator (VELO) detector will use hybrid pixel detectors composed of silicon sensors bump-bonded to new VeloPix CMOS readout chips designed for the new 40MHz readout rate. We will present a novel way of delivering bias through the ASIC backside in order to test IV characteristics of sensors in vacuum before module construction. The appropriate laboratory setups developed to test VELO hybrids for production will also be discussed.
id cern-2314659
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2018
record_format invenio
spelling cern-23146592019-09-30T06:29:59Zhttp://cds.cern.ch/record/2314659engFranco Lima, ViniciusIV Characterisation for the VELO UpgradeLHCb is a dedicated heavy flavour physics experiment that operates at the LHC. The LHCb collaboration plans to change key features of the present detectors for Run III, moving to a full detector readout at 40MHz and operating at a luminosity of 1-2x1033cm-2s-1. The new Vertex Locator (VELO) detector will use hybrid pixel detectors composed of silicon sensors bump-bonded to new VeloPix CMOS readout chips designed for the new 40MHz readout rate. We will present a novel way of delivering bias through the ASIC backside in order to test IV characteristics of sensors in vacuum before module construction. The appropriate laboratory setups developed to test VELO hybrids for production will also be discussed. Poster-2018-626oai:cds.cern.ch:23146592018-02-28
spellingShingle Franco Lima, Vinicius
IV Characterisation for the VELO Upgrade
title IV Characterisation for the VELO Upgrade
title_full IV Characterisation for the VELO Upgrade
title_fullStr IV Characterisation for the VELO Upgrade
title_full_unstemmed IV Characterisation for the VELO Upgrade
title_short IV Characterisation for the VELO Upgrade
title_sort iv characterisation for the velo upgrade
url http://cds.cern.ch/record/2314659
work_keys_str_mv AT francolimavinicius ivcharacterisationfortheveloupgrade