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HLS4ML: deploying deep learning on FPGAs for L1 trigger and Data Acquisition
<!--HTML--><p>Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software,...
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| Lenguaje: | eng |
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2018
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| Acceso en línea: | http://cds.cern.ch/record/2315491 |