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Accessing Intel FPGAs for Acceleration

<!--HTML--><p>In this presentation, we will discuss the latest tools and products from Intel that enables FPGAs to be deployed as Accelerators. We will first talk about the Acceleration Stack for Intel Xeon CPU with FPGAs which makes it easy to create, verify, and execute functions on th...

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Autor principal: Qi, Karl
Lenguaje:eng
Publicado: 2018
Materias:
Acceso en línea:http://cds.cern.ch/record/2319264
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author Qi, Karl
author_facet Qi, Karl
author_sort Qi, Karl
collection CERN
description <!--HTML--><p>In this presentation, we will discuss the latest tools and products from Intel that enables FPGAs to be deployed as Accelerators. We will first talk about the Acceleration Stack for Intel Xeon CPU with FPGAs which makes it easy to create, verify, and execute functions on the Intel Programmable Acceleration Card in a Data Center. We will then talk about the OpenCL flow which allows parallel software developers to create FPGA systems and deploy them using the OpenCL standard. Next, we will talk about the Intel High-Level Synthesis compiler which can convert C++ code into custom RTL code optimized for Intel FPGAs. Lastly, we will focus on the task of running Machine Learning inference on the FPGA leveraging some of the tools we discussed.</p> <p><strong>About the speaker</strong></p> <p>Karl Qi is Sr. Staff Applications Engineer, Technical Training. He has been with the Customer Training department at Altera/Intel for 8 years. Most recently, he is responsible for all training content relating to High-Level Design tools, including the OpenCL SDK, HLS Compiler, and DSP Builder as well as Machine Learning applications. Prior to joining Altera/Intel, he was with Lockheed Martin Space Systems. Overall he has 15 years experience with FPGAs.</p>
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spelling cern-23192642022-11-02T22:27:56Zhttp://cds.cern.ch/record/2319264engQi, KarlAccessing Intel FPGAs for AccelerationAccessing Intel FPGAs for AccelerationCERN Computing Seminar<!--HTML--><p>In this presentation, we will discuss the latest tools and products from Intel that enables FPGAs to be deployed as Accelerators. We will first talk about the Acceleration Stack for Intel Xeon CPU with FPGAs which makes it easy to create, verify, and execute functions on the Intel Programmable Acceleration Card in a Data Center. We will then talk about the OpenCL flow which allows parallel software developers to create FPGA systems and deploy them using the OpenCL standard. Next, we will talk about the Intel High-Level Synthesis compiler which can convert C++ code into custom RTL code optimized for Intel FPGAs. Lastly, we will focus on the task of running Machine Learning inference on the FPGA leveraging some of the tools we discussed.</p> <p><strong>About the speaker</strong></p> <p>Karl Qi is Sr. Staff Applications Engineer, Technical Training. He has been with the Customer Training department at Altera/Intel for 8 years. Most recently, he is responsible for all training content relating to High-Level Design tools, including the OpenCL SDK, HLS Compiler, and DSP Builder as well as Machine Learning applications. Prior to joining Altera/Intel, he was with Lockheed Martin Space Systems. Overall he has 15 years experience with FPGAs.</p>oai:cds.cern.ch:23192642018
spellingShingle CERN Computing Seminar
Qi, Karl
Accessing Intel FPGAs for Acceleration
title Accessing Intel FPGAs for Acceleration
title_full Accessing Intel FPGAs for Acceleration
title_fullStr Accessing Intel FPGAs for Acceleration
title_full_unstemmed Accessing Intel FPGAs for Acceleration
title_short Accessing Intel FPGAs for Acceleration
title_sort accessing intel fpgas for acceleration
topic CERN Computing Seminar
url http://cds.cern.ch/record/2319264
work_keys_str_mv AT qikarl accessingintelfpgasforacceleration