Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a m...

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Detalles Bibliográficos
Autores principales: Pacher, L., Monteil, E., Demaria, N., Rivetti, A., Da Rocha Rolo, M., Dellacasa, G., Mazza, G., Rotondo, F., Wheadon, R., Paternò, A., Panati, S., Loddo, F., Licciulli, F., Ciciriello, F., Marzocca, C., Gaioni, L., Traversi, G., Re, V., De Canio, F., Ratti, L., Marconi, S., Placidi, P., Magazzù, G., Stabile, A., Mattiazzo, S.
Formato: info:eu-repo/semantics/article
Lenguaje:eng
Publicado: Proceedings of Science 2018
Materias:
Detectors and Experimental Techniques
4: Micro-electronics and interconnections
Acceso en línea:http://cds.cern.ch/record/2319291

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