Phase-II Associative Memory ASIC Specifications

This documents defines the specifications for the Associative Memory ASIC for Phase-II. The work-flow toward the final ASIC is organized in the following three steps • AM08 prototype: small area MPW prototype to test all the full custom features, the VHDL logic and the I/O. This chip must be fully f...

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Detalles Bibliográficos
Autores principales: Stabile, Alberto, Annovi, Alberto, Warren, Matthew, Green, Barry, Konstantinidis, Nikolaos, Motuk, Halil Erdem, Frontini, Luca, Liberali, Valentino, Crescioli, Francesco, Fedi, Giacomo, Sotiropoulou, Calliope-louisa, De Canio, Francesco, Traversi, Gianluca, Shojaii, Seyed Ruhollah, Kubota, Takashi, Calderini, Giovanni, Palla, Fabrizio, Checcucci, Bruno, Spiller, Laurence Anthony, Mcnamara, Peter Charles
Lenguaje:eng
Publicado: 2018
Materias:
Engineering
Acceso en línea:http://cds.cern.ch/record/2320701
Descripción
Sumario:This documents defines the specifications for the Associative Memory ASIC for Phase-II. The work-flow toward the final ASIC is organized in the following three steps • AM08 prototype: small area MPW prototype to test all the full custom features, the VHDL logic and the I/O. This chip must be fully functional with smaller memory area than the final ASIC; • AM09pre pre-production: full area ASIC to be fabricated with a full-mask set pilot run. Production corner wafers will be created; • AM09 production: full area ASIC with refinements for the mass production. The AM09 will be developed built on the AM08 extending the memory area, therefore the specification of both versions must be compatible.

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